Prompt Description

This paper presents a novel 12-transistor transmission gate-based low-power (TGLP12T) SRAM memory cell utilizing carbon nanotube FETs (CNTFETs) for battery-operated implantable medical devices at 32 nm technology. The cell core addresses half-select issues prevalent in conventional SRAM arrays by employing a single-ended read/write architecture, thereby facilitating bit interleaving. The design incorporates stacked NCNTFETs in its pull-down network to enhance write ability and write noise margin, and PCNTFETs in the pull-up path to suppress leakage power. A fully decoupled read path improves the read static noise margin (RSNM), while transmission gate-controlled access transistors and core inverter stacking contribute to reduced dynamic and static power consumption. Comprehensive HSPICE simulations using the Stanford CNTFET model validate the TGLP12T cell's performance.